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SkyWater
SkyWater SKY130 PDK
Table Of Contents
Versioning Information
Current Status
Known Issues
Design Rules
Background
Masks
Criteria & Assumptions
Layers Reference
Device and Layout vs. Schematic
Summary of Key Periphery Rules
Periphery Rules
WLCSP Rules
High Voltage Methodology
Very High Voltage Methodology
Antenna Rules
Parasitic Layout Extraction
Device Details
Error Messages
PDK Contents
Libraries
SkyWater Foundry Provided Standard Cell Libraries
sky130
_
fd
_
io
- SKY130 IO and periphery cells (SkyWater Provided)
User Guide for
sky130
_
fd
_
io
Critical Requirements Summary
File Types
Analog Design
With Cadence Virtuoso
With MAGIC
With Klayout
With Berkeley Analog Generator (BAG)
With FASoC
With your design flow?
Digital Design
With Cadence Innovus
With OpenROAD
With your design flow?
Simulation
With Cadence Spectre
With ngspice
With your design flow?
Physical & Design Verification
Automated Design Rule (DRC) Checking
With Mentor Calibre
With Magic
With KLayout
Layout Versus Schematic (LVS) Checking
With Mentor Calibre
With Magic
With KLayout
Parasitic Extraction (PEX)
With Mentor Calibre
With Magic
With KLayout
Python API
skywater_pdk package
Previous Nomenclature
Glossary
How to Contribute
Partners
SkyWater SKY130 PDK
Table Of Contents
Versioning Information
Current Status
Known Issues
Design Rules
Background
Masks
Criteria & Assumptions
Layers Reference
Device and Layout vs. Schematic
Summary of Key Periphery Rules
Periphery Rules
WLCSP Rules
High Voltage Methodology
Very High Voltage Methodology
Antenna Rules
Parasitic Layout Extraction
Device Details
Error Messages
PDK Contents
Libraries
SkyWater Foundry Provided Standard Cell Libraries
sky130
_
fd
_
io
- SKY130 IO and periphery cells (SkyWater Provided)
User Guide for
sky130
_
fd
_
io
Critical Requirements Summary
File Types
Analog Design
With Cadence Virtuoso
With MAGIC
With Klayout
With Berkeley Analog Generator (BAG)
With FASoC
With your design flow?
Digital Design
With Cadence Innovus
With OpenROAD
With your design flow?
Simulation
With Cadence Spectre
With ngspice
With your design flow?
Physical & Design Verification
Automated Design Rule (DRC) Checking
With Mentor Calibre
With Magic
With KLayout
Layout Versus Schematic (LVS) Checking
With Mentor Calibre
With Magic
With KLayout
Parasitic Extraction (PEX)
With Mentor Calibre
With Magic
With KLayout
Python API
skywater_pdk package
Previous Nomenclature
Glossary
How to Contribute
Partners
Index
Symbols
|
A
|
C
|
D
|
E
|
L
|
M
|
N
|
O
|
P
|
Q
|
R
|
S
|
V
|
Y
Symbols
.lef
.lib
A
Antenna Rule Violations
Apache 2.0 license
C
CALMA
Calma
Calma Format
Caltech Intermediate Form
CCS
ce
CIF
Cypress
Cypress Technologies
D
Design Rule Check
Design Rule Checking
DRC
E
ECSM
Electro-Static Discharge (protection from)
ESD
L
Layout Verse Schematic
LEF
Liberty Models
Liberty Timing Models
Liberty Wire Load Models
Library Exchange Format
license
Linear ASICs
LVS
M
MAGIC
Mentor
Mentor Calibre
Mentor Graphics
MIM
MiM
MiM caps
MoM
MoM caps
N
ngspice
NLDM
O
OPen HardWare
OpenRoad
OPHW
OSU
P
Parasitic Extraction
PEX
Place aNd Route
PNR
Q
qflow
R
Register Transfer Language
RTL
S
s180
s8
s8_osu130
s8_schd
s8iom0s8
s8pfhd
s8pfn-20
s8phirs
s8phirs_10r
s8phrc
sc
scs8hd
SkyWater
SkyWater S8
SkyWater SKY130 process
SkyWater SKY130 technology
SkyWater Technology
STA
Standard Cell
Static Timing Analysis
V
Very Large Scale Integration
VLSI
VLSI System Design
VPP
VPP capacitor
VSD
Y
yosys