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SkyWater SKY130 Process Design Rules¶
Process Design Rules¶
- Background
- Masks
- Criteria & Assumptions
- Layers Reference
- Device and Layout vs. Schematic
- Summary of Key Periphery Rules
- Periphery Rules
- (x.-)
- (dnwell.-)
- (nwell.-)
- (pwbm.-)
- (pwdem.-)
- (hvtp.-)
- (hvtr.-)
- (lvtn.-)
- (ncm.-)
- (difftap.-)
- (tunm.-)
- (poly.-)
- (rpm.-)
- (varac.-)
- (photo.-)
- (npc.-)
- (n/ psd.-)
- (licon.-)
- (li.-.-)
- (ct.-)
- (capm.-)
- (vpp.-)
- (m1.-)
- (via.-)
- (m2.-)
- (via2.-)
- (m3.-)
- (via3.-)
- (nsm.-)
- (indm.-)
- (m4.-)
- (via4.-)
- (m5.-)
- (pad.-)
- (rdl.-)
- (mf.-)
- (hvi.-)
- (hvnwell.-)
- (hvdifftap.-)
- (hvpoly.-)
- (hvntm.-)
- (denmos.-)
- (depmos.-)
- (extd.-)
- (hv.-.-)
- (vhvi.-.-)
- (uhvi.-.-)
- (ulvt-.-)
- (pwres.-.-)
- (rfdiode.-.-)
- WLCSP Rules
- High Voltage Methodology
- Very High Voltage Methodology
- Antenna Rules
- Parasitic Layout Extraction
- Device Details
- MiM Capacitor
- Varactors
- Vertical Parallel Plate (VPP) capacitors
- Diodes
- NMOS ESD FET
- 5.0V/10.5V NMOS FET
- 11V/16V NMOS FET
- 1.8V low-VT NMOS FET
- 1.8V NMOS FET
- 3.0V native NMOS FET
- 5.0V native NMOS FET
- 20V NMOS FET
- 20V isolated NMOS FET
- 20V native NMOS FET
- 20V NMOS zero-VT FET
- Bipolar (NPN)
- 5.0V/10.5V PMOS FET
- 10V/16V PMOS FET
- 1.8V high-VT PMOS FET
- 1.8V low-VT PMOS FET
- 1.8V PMOS FET
- 20V PMOS FET
- Bipolar (PNP)
- Generic Resistors
- P+ poly precision resistors
- P- poly precision resistors
- SONOS cells
- SRAM cells
- Error Messages